Meet Your Power, Performance, Area, and Schedule Targets

Design Excellence

Create and package the biggest, most complex digital SoCs, and the fastest, most compact analog/RFICs. Leading-edge semiconductor integrated circuits (IC) drive the electronics systems that are changing our lives. They are the enabling technology that is transforming everything from home automation to self-driving cars and advanced health care. Develop your design with optimal performance, power, and area (PPA) to create innovative system functionality.

Product Groups

Digital Design and Signoff

CadenceĀ® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.


  • Logic Equivalence Checking
  • SoC Implementation and Floor planning
  • Functional ECO
  • Low-Power Validation
  • Synthesis
  • Power Analysis
  • Constraints and CDC Signoff
  • Silicon Signoff and Verification
  • Library Characterization
  • Test


  • Cadence Certus Closure Solution
  • Integrity 3D-IC Platform
  • Cadence Cerebrus Intelligent Chip Explorer
  • Genus Synthesis Solution
  • Innovus Implementation System
  • Tempus Timing Signoff Solution
  • Voltus IC Power Integrity Solution
  • Pegasus Verification System

Custom IC / Analog / RF Design

CadenceĀ® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.


  • Circuit Design
  • Circuit Simulation
  • Layout Design
  • Layout Verification
  • Library Characterization
  • RF / Microwave Solutions


  • Spectre X Simulator
  • Spectre FX Simulator
  • Virtuoso Layout Suite
  • Virtuoso ADE Product Suite
  • Virtuoso Advanced Node
  • Voltus-XFi Custom Power integrity Solution


Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry.


  • Simulation
  • AI-Driven Verification
  • Emulation and Prototyping
  • Static and Formal Verification
  • Verification IP
  • Debug
  • Portable Stimulus
  • System VIP
  • Virtual and Hybrid Platform
  • Functional Safety
  • Planning and Management


  • Verisium Manager
  • Verisium Debug
  • Verisium AI-Driven Verification
  • Jasper RTL Apps
  • Jasper C Apps
  • Helium Virtual and Hybrid Studio
  • Xcelium Logic Simulation
  • Palladium Enterprise Emulation
  • Protium Enterprise Prototyping
  • System VIP
  • Midas Safety Platform


An open IP platform for you to customize your app-driven SoC design.


  • 112G/56G SerDes
  • Chiplet and D2D
  • Denali Memory Interface and Storage IP
  • Interface IP
  • PCIe and CXL
  • Tensilica Processor IP

IC Package Design and Analysis

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, CadenceĀ® package implementation products deliver the automation and accuracy.


  • Cross-Platform Co-Design and Analysis
  • IC Package Design
  • SI/PI Analysis for IC Packaging
  • SI/PI Analysis Point Tools for IC Packaging
  • IC Package Design Flows